Multithreading

1. Instruction Issue

• Regular instruction issue has reduced utilisation due to stalls and dependencies.
• Superscalar issue leads to more performance, but less utilisation.
• Chip multiprocessing (CMP) increases utilisation by adding more cores, but does not improve single thread performance.
• Fine Grained Multithreading (FGMT) switches between threads every cycle to reduce stalls. However, intra-thread dependencies still cause stalls.
• Simultaneous Multithreading (SMT) allows instructions from multiple threads to be issued in the same cycle, increasing utilisation further.

2. Simultaneous Multithreading (SMT)

In an SMT pipeline, there would be program counters and register decode maps, increasing overall utilisation. However, this means:

• Each individual thread runs slower due to resource sharing.
• Threads contend for resources possibly symbiotically, but often destructively (cache trashing, TLB thrashing, ...).
• Need to determine which resources are shared and which are private.
• SMT threads must be scheduled fairly, avoid starvation.
• Side channel threat.

SMT threads exploit memory-system parallelism by allowing multiple threads to issue memory operations simultaneously. This is called latency hiding, overlapping data access with compute. However, increasing SMT threads has overhead due to handling more registers (register renaming), more complex scheduling, and increased contention.

On Intel, this is called Hyper-Threading.